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october 2008 dsc-6109/0a ?2005 integrated device technology, inc. qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron technology, inc. 1 18mb pipelined qdr?ii sram burst of 2 idt71p72804 idt71p72604 description the idt qdrii tm burst of two srams are high-speed synchro- nous memories with independent, double-data-rate (ddr), read and write data ports. this scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write. four data word transfers occur per clock cycle, providing quad-data-rate (qdr) performance. comparing this with standard sram common i/o (cio), single data rate (sdr) de- vices, a four to one increase in data access is achieved at equivalent clock speeds. considering that qdrii allows clock speeds in excess of standard sram devices, the throughput can be increased well beyond four to one in most applications. using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. all buses associated with the qdrii are unidirectional and can be optimized for signal integrity at very high bus speeds. the qdrii has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. the qdrii has a single ddr address bus with multiplexed read and write addresses. all read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. the read and write enables are received on the first half of the clock cycle. the byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. functional block diagram notes 1) represents 18 signal lines for x18, and 36 signal lines for x36 2) represents 19 address signal lines for x18, and 18 address signal lines for x36. 3) represents 2 signal lines for x18, and 4r signal lines for x36. 4) represents 36 signal lines for x18, and 72 signal lines for x36. add reg ctrl logic clk gen (note2) sa r w (note3) bw x k k c c select output control w r i t e / r e a d d e c o d e s e n s e a m p s o u t p u t r e g o u t p u t s e l e c t write driver (note4) (note2) cq q (note1) (note4) 18m memory array cq data reg (note1) (note1) 6109 drw 16 data reg (note1) d features 18mb density (1mx18, 512kx36) separate, independent read and write data ports - supports concurrent transactions dual echo clock output 2-word burst on all sram accesses ddr (double data rate) multiplexed address bus - one read and one write request per clock cycle ddr (double data rate) data buses - two word burst data per clock on each port - four word transfers per clock cycle (2 word bursts on 2 ports) depth expansion through control logic hstl (1.5v) inputs that can be scaled to receive signals from 1.4v to 1.9v. scalable output drivers - can drive hstl, 1.8v ttl or any voltage level from 1.4v to 1.9v. - output impedance adjustable from 35 ohms to 70 ohms commercial and industrial temperature ranges 1.8v core voltage (v dd ) 165-ball, 1.0mm pitch, 13mm x 15mm fbga package jtag interface
6.42 2 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 clocking the qdrii sram has two sets of input clocks, namely the k, k clocks and the c, c clocks. in addition, the qdrii has an output ?echo? clock, cq, cq . the k and k clocks are the primary device input clocks. the k clock is, used to clock in the control signals ( r , w and bw x), the read ad- dress, and the first word of the data burst during a write operation. the k clock is used to clock in the control signals ( bw x), write address and the second word of the data burst during a write operation. the k and k clocks are also used internally by the sram. in the event that the user disables the c and c clocks, the k and k clocks will also be used to clock the data out of the output register and generate the echo clock. the c and c clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. c and c must be presented to the sram within the timing tolerances. the output data from the qdrii will be closely aligned to the c and c input, through the use of an internal dll. when c is presented to the qdrii sram, the dll will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the c clock. the c clock and second data word of the burst will also correspond. single clock mode the qdrii sram may be operated with a single clock pair. c and c may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the k and k clocks. dll operation the dll in the output structure of the qdrii sram can be used to closely align the incoming clocks c and c with the output of the data, generating very tight tolerances between the two. the user may disable the dll by holding doff low. with the dll off, the c and c (or k and k if c and c are not used) will directly clock the output register of the sram. with the dll off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. the qdrii has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. the user can use the echo clock for downstream clocking of the data. echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal quali- ties to guarantee data capture. since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. all interfaces of the qdrii sram are hstl, allowing speeds be- yond sram devices that use any form of ttl interface. the interface can be scaled to higher voltages (up to 1.9v) to interface with 1.8v systems if necessary. the device has a v ddq and a separate vref, allowing the user to designate the interface operational voltage, inde- pendent of the device core voltage of 1.8v v dd . the output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. the device is capable of sustaining full bandwidth on both the input and output ports simultaneously. all data is in two word bursts, with addressing capability to the burst level. echo clock the echo clocks, cq and cq , are generated by the c and c clocks (or k, k if c, c are disabled). the rising edge of c generates the rising edge of cq, and the falling edge of cq . the rising edge of c generates the rising edge of cq and the falling edge of cq. this scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. the echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. read and write operations qdrii devices internally store the two words of the burst as a single, wide word and will retain their order in the burst. there is no ability to address to the single word level or reverse the burst order; however, the byte and nibble write signals can be used to prevent writing any indi- vidual bytes, or combined to prevent writing one word of the burst. read operations are initiated by holding the read port select ( r ) low, and presenting the read address to the address port during the rising edge of k which will latch the address. the data will then be read and will appear at the device output at the designated time in correspondence with the c and c clocks. write operations are initiated by holding the write port select ( w ) low and designating with the byte write inputs ( bw x) which bytes are to be written. the first word of the data must also be present on the data input bus d[x:0]. upon the rising edge of k the first word of the burst will be latched into the input register. after k has risen, and the designated hold times observed, the second half of the clock cycle is initiated by present- ing the write address to the address bus sa[x:0], the bw x inputs for the second data word of the burst, and the second data item of the burst to the data bus d[x:0]. upon the rising edge of k , the second word of the burst will be latched, along with the designated address. both the first and second words of the burst will then be written into memory as designated by the address and byte write enables. output enables the qdrii sram automatically enables and disables the q[x:0] outputs. when a valid read is in progress, and data is present at the output, the output will be enabled. if no valid data is present at the output (read not active), the output will be disabled (high impedance). the echo clocks will remain valid at all times and cannot be disabled or turned off. during power-up the q outputs will come up in a high impedance state. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and vss to allow the sram to adjust its output drive imped- ance. the value of rq must be 5x the value of the intended drive impedance of the sram. the allowable range of rq to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with v ddq = 1.5v. the output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and tem- perature. if the user wishes to drive the output impedance of the sram to it?s lowest value, the zq pin may be tied to v ddq .
6.42 3 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 symbol pin function description d[x:0] input synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations 1m x 18 -- d[17:0] 512k x 36 -- d[35:0] bw 0 , bw 1 bw 2 , bw 3 input synchronous byte write select 0, 1, 2, and 3 are active low. sampled on the rising edge of the k and again on the rising edge of k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. all the byte writes are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written in to the device. 1m x 18 -- bw 0 controls d[8:0] and bw 1 controls d[17:9] 512k x 36 -- bw 0 controls d[8:0], bw 1 controls d[17:9], bw 2 controls d[26:18] and bw 3 controls d[35:27] sa input synchronous address inputs. read addresses are sampled on the rising edge of k clock during active read operations. write addresses are sampled on the rising edge of k clock during active write operations. these address inputs are multiplexed, so that both a read and write operation can occur on the same clock cycle. these inputs are ignored when the appropriate port is deselected. q[x:0] output synchronous data output signals. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k when operating in single clock mode. when the read port is deselected, q[x:0] are automatically three-stated. w input synchronous write control logic active low. sampled on the rising edge of the positive input clock (k). when asserted active, a write operation in initiated. deasserting will deselect the write port. deselecting the write port will cause d[x:0] to be ignored. r input synchronous read control logic, active low. sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the c clock. each read access consists of a burst of two sequential transfer. c input clock positive output clock input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input clock negative output clock input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input clock positive input clock input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q[x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q[x:0] when in single clock mode. cq, cq output clock synchronous echo clock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals are free running and do not stop when the output data is tri- stated. zq inp ut output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. q[x:0] output impedance is set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. 6109 tbl 02a pin definitions
6.42 4 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 symbol pin function description doff input dll turn off. when low this input will turn off the dll inside the device. the ac timings with the dll turned off will be different from those listed in this data sheet. there will be an increased propagation delay from the incidence of c and c to q, or k and k to q as configured. the propagation delay is not a tested parameter, but will be similar to the propagation delay of other sram devices in this speed grade. tdo output tdo pin for jtag tck inp ut tck p in fo r jtag. tdi input tdi pin for jtag. an internal resistor will pull tdi to v dd when the pin is unconnected. tms input tms pin for jtag. an internal resistor will pull tms to v dd when the pin is unconnected. nc no connect no connects inside the package. can be tied to any voltage level v ref input reference reference voltage input. static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device. should be connected to a 1.8v power supply. v ss ground ground for the device. should be connected to ground of the system. v ddq power supply power supply for the outputs of the device. should be connected to a 1.5v power supply for hstl or scaled to the desired output voltage. 6109 tbl 02b pin definitions continued
6.42 5 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 pin configuration idt71p72804 (1m x 18) 165-ball fbga pinout top view 1234567891011 a cq v ss/ sa (3) nc/ sa (1) wbw 1 k nc r sa v ss / sa (2) cq b nc q 9 d 9 sa nc k bw 0 sa nc nc q 8 c nc nc d 10 v ss sa sa sa v ss nc q 7 d 8 d nc d 11 q 10 v ss v ss v ss v ss v ss nc nc d 7 e nc nc q 11 v ddq v ss v ss v ss v ddq nc d 6 q 6 f nc q 12 d 12 v ddq v dd v ss v dd v ddq nc nc q 5 g nc d 13 q 13 v ddq v dd v ss v dd v ddq nc nc d 5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d 14 v ddq v dd v ss v dd v ddq nc q 4 d 4 k nc nc q 14 v ddq v dd v ss v dd v ddq nc d 3 q 3 l nc q 15 d 15 v ddq v ss v ss v ss v ddq nc nc q 2 m nc nc d 16 v ss v ss v ss v ss v ss nc q 1 d 2 n nc d 17 q 16 v ss sa sa sa v ss nc nc d 1 p nc nc q 17 sa sa c sa sa nc d 0 q 0 r tdo tck sa sa sa c sa sa sa tms tdi 6109 tbl 12b notes: 1. a3 is reserved for the 36mb expansion address. 2. a10 is reserved for the 72mb expansion address. this must be tied or driven to vss on the 1m x 18 qdrii burst of 2 (71p728 04) devices. 3. a2 is reserved for the 144mb expansion address. this must be tied or driven to vss on the 1m x 18 qdrii burst of 2 (71p72 804) devices.
6.42 6 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 pin configuration idt71p72604 (512k x 36) 165-ball fbga pinout top view 1234567891011 a cq v ss/ sa (4) nc/ sa (2) wbw 2 kbw 1 r nc/ sa (1) v ss/ sa (3) cq b q 27 q 18 d 18 sa bw 3 k bw 0 sa d 17 q 17 q 8 c d 27 q 28 d 19 v ss sa sa sa v ss d 16 q 7 d 8 d d 28 d 20 q 19 v ss v ss v ss v ss v ss q 16 d 15 d 7 e q 29 d 29 q 20 v ddq v ss v ss v ss v ddq q 15 d 6 q 6 f q 30 q 21 d 21 v ddq v dd v ss v dd v ddq d 14 q 14 q 5 g d 30 d 22 q 22 v ddq v dd v ss v dd v ddq q 13 d 13 d 5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d 31 q 31 d 23 v ddq v dd v ss v dd v ddq d 12 q 4 d 4 k q 32 d 32 q 23 v ddq v dd v ss v dd v ddq q 12 d 3 q 3 l q 33 q 24 d 24 v ddq v ss v ss v ss v ddq d 11 q 11 q 2 m d 33 q 34 d 25 v ss v ss v ss v ss v ss d 10 q 1 d 2 n d 34 d 26 q 25 v ss sa sa sa v ss q 10 d 9 d 1 p q 35 d 35 q 26 sa sa c sa sa q 9 d 0 q 0 r tdo tck sa sa sa c sa sa sa tms tdi 6109 tbl 12c notes: 1. a9 is reserved for the 36mb expansion address. 2. a3 is reserved for the 72mb expansion address. 3. a10 is reserved for the 144mb expansion address. this must be tied or driven to vss on the 512k x 36 qdrii burst of 2 (71p 72604) devices. 4. a2 is reserved for the 288mb expansion address. this must be tied or driven to vss on the 512k x 36 qdrii burst of 2 (71p 72604) devices.
6.42 7 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 absolute maximum ratings (1) (2) capacitance (ta = +25c, f = 1.0mhz) (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vddq must not exceed vdd during normal operation. note: 1. tested at characterization and retested after any design or process change that may affect these parameters. symbol parameter conditions max. unit c in input capacitance v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7 pf 6109 tbl 06 symbol rating value unit v te rm supply voltage on v dd with respect to gnd ?0.5 to +2.9 v v te rm supply voltage on v ddq with respect to gnd ?0.5 to v dd +0.3 v v te rm voltage on input terminals with respect to gnd. ?0.5 to v dd +0.3 v v te rm voltage on output and i/o term inals with respect to gnd. -0.5 to v ddq +0.3 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out continuous current into outputs + 20 ma 6109 tbl 0 5 recommended dc operating and temperature conditions notes: 1) all byte write ( bw x) signals are sampled on the rising edge of k and again on k . the data that is present on the data bus in the designated byte will be latched into the input if the corresponding bw x is held low. the rising edge of k will sample the first byte of the two word burst and the rising edge of k will sample the second byte of the two word burst. 2) the availability of the bw x on designated devices is de scribed in the pin description table. 3) the qdrii burst of two sram has data forwarding. a read request that is initiated on the same cycle as a write request to the same address will produce the newly written data in response to the read request. signal bw 0 bw 1 bw 2 bw 3 write byte 0 l x x x write byte 1 x l x x write byte 2 x x l x write byte 3 x x x l 6109 tbl 09 write descriptions (1,2,3) symbol parameter min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v ss ground 0 0 0 v v ref input reference voltage 0.68 v ddq /2 0.95 v t a ambient temperature (1) commercial 0 to +70 o c industrial -40 to +85 o c 6109 tbl 04 note: 1. during production testing, the case temperature equals the ambient temperature.
6.42 8 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 application example sram #1 sa wbw 0 bw 1 c q zq 250 ? r d k k c data in r memory controller return clk source clk return clk source clk r=50 ? r v t =v ref r 6109 drw 20 v t v t w address data out r v t r v t r sram #4 sa wbw 0 bw 1 c q zq 250 ? r d k k c r r r bw x
6.42 9 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) parameter symbol test conditions min max unit note input leakage current i il v dd = max v in = v ss to v ddq -2 +2 a output leakage current i ol output disabled -2 +2 a com'l ind operating current (x36): ddr i dd v dd = max, i out = 0ma (outputs open), cycle time > t khkh min 200mh z - 950 1000 ma 1 167mh z - 850 900 operating current (x18): ddr i dd v dd = max, i out = 0ma (outputs open), cycle time > t khkh min 250mh z -850- ma 1,8 200mh z -750800 167mh z -650700 standby current: nop i sb1 device deselected (in nop state), iout = 0ma (outputs open), f=max , all inputs < 0.2v or > vdd -0.2v 250mh z -375- ma 2,8 200mh z -335385 167mh z -300350 output high voltage v oh1 rq = 250 ?, i oh = -15ma v ddq /2-0.12 v ddq /2+0.12 v 3,7 output low voltage v ol1 rq = 250 ?, i ol = 15ma v ddq /2-0.12 v ddq /2+0.12 v 4,7 output high voltage v oh2 i oh = -0.1ma v ddq -0.2 v ddq v5 output low voltage v ol2 i ol = 0.1ma v ss 0.2 v 6 6109 tbl 10c notes: 1. operating current is measured at 100% bus utilization. 2. standby current is only after all pending read and write burst operations are completed. 3. outputs are impedance-controlled. ioh = -(vddq/2)/(rq/5) and is guaranteed by device characterization for 175 ? < rq < 350 ?. this parameter is tested at rq = 250 ?, which gives a nominal 50 ? output impedance. 4. outputs are impedance-controlled. iol = (vddq/2)/(rq/5) and is guaranteed by device characterization for 175 ? < rq < 350 ?. this parameter is tested at rq = 250 ?, which gives a nominal 50 ? output impedance. 5. this measurement is taken to ensure that the output has the capability of pulling to the vddq rail, and is not intended to b e used as an impedance measurement point. 6. this measurement is taken to ensure that the output has the capability of pulling to vss, and is not intended to be used as an impedance measurement point. 7. programmable impedance mode. 8. industrial temperature range is not available for the 250mhz speed grade.
6.42 10 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 input electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) parameter symbol min max unit notes input high voltage, dc v ih (dc )v ref +0.1 v ddq +0.3 v 1,2 input low voltage, dc v il (dc) -0.3 v ref -0.1 v 1,3 input high voltage, ac v ih (ac) v ref +0.2 - v 4,5 input low voltage, ac v il (ac) -v ref -0.2 v 4,5 6109 tbl 10d notes: 1.these are dc test criteria. dc design criteria is vref + 50mv. the ac vih/vil levels are defined separately for measuring timing param eters. 2. vih (max) dc = vddq+0.3, vih (max) ac = vdd +0.5v (pulse width <20% tkhkh (min)) 3. vil (min) dc = -0.3v, vil (min) ac = -0.5v (pulse width <20% tkhkh (min)) 4. this conditon is for ac function test only, not for ac parameter test. 5. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through the target ac level, vil(ac) or vih(ac) b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, vil(dc) or vih(dc) v ss v ih v ss -0.25v v ss -0.5v 20% tkhkh (min) 6109 drw 2 2 v il v dd v dd +0.25 v dd +0.5 2 0 % t k h k h ( m i n ) 6109 drw 2 1 overshoot timing undershoot timing
6.42 11 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 ac test load device r l =50 ? z 0 =50 ? v ddq /2 under test v ref output 6109 drw 04 zq r q =250 ? ddq /2 v parameter symbol value unit core power supply voltage v dd 1.7 to 1.9 v i/o power supply voltage v ddq 1.4 to v dd v input high level v ih (v ddq /2)+ 0.5 v input low level v il (v ddq /2)- 0.5 v inp ut re fe re nce le ve l vref v ddq /2 v input rise/fall time tr/tf 0.3/0.3 ns output timing reference level v ddq /2 v 6109tbl 11a ac test conditions (1) note: 1. parameters are tested with rq=250 ? ( v ddq /2) + 0.5v (v ddq /2) - 0.5v 6109 drw 06 v ddq /2 v ddq /2 test points input waveform output waveform 6109 drw 06a v ddq /2 v ddq /2 test points
6.42 12 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 ac electrical characteristics (vdd = 1.8 100mv, vddq = 1.4v to 1.9v, commercial and industrial temperature ranges) (3,7) (3,7) (3,7) (3,7) (3,7) symbol parameter 250mhz (10,11) 200mhz 167mhz unit notes min. max min. max min. max clock parameters t khkh clock cycle time (k , k ,c, c ) 4.00 6.30 5.00 7.88 6.00 8.40 ns t kc var clock phase jitter (k, k ,c, c ) - 0.20 - 0.20 - 0.20 ns 1,5 t khkl clock high time (k, k ,c, c ) 1.60 - 2.00 - 2.40 - ns 8 t klkh clock low time (k, k ,c, c ) 1.60 - 2.00 - 2.40 - ns 8 t kh k h clock to clock (k k ,c c ) 1.80 - 2.20 - 2.70 - ns 9 t k hkh clock to clock ( k k, c c) 1.80 - 2.20 - 2.70 - ns 9 t khch clock to data clock (k c, k c ) 0.00 1.80 0.00 2.30 0.00 2.80 ns t kc lock dll lock time (k, c) 1024 - 1024-1024-cycles2 t kc reset k static to dll reset 30 -30-30-ns output parameters t chqv c, c high to o utp ut valid - 0.45 - 0.45 - 0.50 ns 3 t chqx c, c high to o utp ut ho ld -0.45 - -0.45 - -0.50 - ns 3 t chcqv c, c high to echo clock valid - 0.45 - 0.45 - 0.50 ns 3 t chcqx c, c high to echo clock hold -0.45 - -0.45 - -0.50 - ns 3 t cqhqv cq, cq high to output valid - 0.30 - 0.35 - 0.40 ns t cqhqx cq, cq high to output hold -0.30 - -0.35 - -0.40 - ns t chqz c high to output high-z - 0.45 - 0.45 - 0.50 ns 3,4,5 t chqx1 c high to output low-z -0.45 - -0.45 - -0.50 - ns 3,4,5 set-up times t avkh address valid to k, k rising edge 0.35 - 0.40 - 0.50 - ns 6 t ivkh r , w inputs valid to k, k rising edge 0.35 - 0.40 - 0.50 - ns t dvkh data-in and bwx valid to k, k rising edge 0.35 - 0.40 - 0.50 - ns hold times t khax k, k rising edge to address hold 0.35 - 0.40 - 0.50 - ns 6 t khix k, k rising edge to r , w inputs hold 0.35 - 0.40 - 0.50 - ns t khdx k, k rising edge to data-in and bwx hold 0.35 - 0.40 - 0.50 - ns 6109 tbl 11 notes: 1. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. vdd slew rate must be less than 0.1v dc per 50 ns for dll lock retention. dll lock time begins once vdd and input clock ar e stable. 3. if c, c are tied high, k, k become the references for c, c timing parameters. 4. to avoid bus contention, at a given voltage and temperature tchqx1 is bigger than tchqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worse case at totally different te st conditions (0c, 1.9v) than tchqz, which is a max parameter (worst case at 70c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. this parameter is guaranteed by device characterization, but not production tested. 6. all address inputs must meet the specified setup and hold times for all latching clock edges. 7. during production testing, the case temperature equals ta. 8. clock high time (tkhkl) and clock low time (tklkh) should be within 40% to 60% of the cycle time (tkhkh). 9. clock to clock time (tkh k h) and clock to clock time (t k hkh) should be within 45% to 55% of the cycle time (tkhkh). 10. the 250mhz speed grade is not available in the 512k x 36-bit option. 11. industrial temperature range is not available for the 250mhz speed grade.
6.42 13 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 timing waveform of combined read and write cycles 6109 drw 09a k k 1 2 3 r sa q tkhch tkhkl tkhix tivkh tkhax tavkh c c cq cq tchqx tchqx1 tklkh tchcqv tchcqx w d tkhdx tdvkh 4 5 6 7 8 9 10 tklkh tkhkh tkh k h a0 a3 a2 a1 a4 a5 a6 tkhax tavkh d10 d11 d30 d31 d50 d51 d60 d61 tkhdx tdvkh q00 q01 q20 q21 q40 q41 tchqz tchqv tchqv tchqx tcqhqv tkhch tkhkl tkh k h tkhkh tchcqx tchcqv read a0 write a1 read a2 read a4 nop nop nop write a3 write a5 write a6 tcqhqx
6.42 14 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 this part contains an ieee standard 1149.1 compatible test ac- cess port (tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. in conformance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass regis- ter and id register. the tap controller has a standard 16-state machine that resets internally upon power-up; therefore, the trst signal is not jtag block diagram jtag instruction coding ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 0 0 1 idcode id entificatio n reg ister 2 0 1 0 sample-z boundary scan register 1 0 1 1 reserved do not use 5 1 0 0 sample/preload boundary scan register 4 1 0 1 reserved do not use 5 1 1 0 reserved do not use 5 1 1 1 bypass bypass register 3 6109tbl 13 notes: 1. places qs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initialized to vss when bypass instruction is in voked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction does not place output pins in hi-z. 5. this instruction is reserved for future use. tap controller state diagram test logic reset run test idle select dr capture dr pause dr exit 2 dr update dr shift dr exit 1 dr select ir capture ir pause ir exit 2 ir update ir shift ir exit 1 ir 0 0 0 0 0 0 1 1 1 1 1 1 1 0 6109 drw 17 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 sram core bypass reg. identification reg. instruction reg . control signal s tap controller a,d k, k c,c q cq cq tdi tms tck td o 6109 drw 18 s ieee 1149.1 test access port and boundary scan-jtag required. it is possible to use this device without utilizing the tap. to disable the tap controller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude a mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to v dd through a resistor. tdo should be left unconnected.
6.42 15 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bit 32 bits 107 bits 1mx18 3 bits 1 bit 32 bits 107 bits 6109 tbl 14 instruction field all devices description part number revision number (31:29) 0x0 revision number device id (28:12) 0x0284 0x0285 512kx36 qdrii burst of 2 1mx18 71p72604s 71p72804s idt jedec id code (11:1) 0x033 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. 6109 tbl 15 scan register definition identification register definitions
6.42 16 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 boundary scan exit order order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e 6109 tbl 16 order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 inte rnal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 1h 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d 6109 tbl 17 order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1j 85 2j 86 3k 87 3j 88 2k 89 1k 90 2l 91 3l 92 1m 93 1l 94 3n 95 3m 96 1n 97 2m 98 3p 99 2n 100 2p 101 1p 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r 6109 tbl 18
6.42 17 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 parameter symbol min ty p max unit note i/o power supply v ddq 1.4 - v dd v power supply voltage v dd 1.7 1.8 1.9 v inp ut hig h le ve l v ih 1.3 - v dd +0.3 v inp ut lo w le ve l v il -0.3 - 0.5 v tck input leakage current i il -5 - +5 a tms, tdi input leakage current i il -15 - +15 a tdo output leakage current i 0l -5 - +5 a output high voltage (i oh = -1ma) v oh v ddq - 0.2 - v ddq v1 output low voltage (i ol = 1ma) v ol v ss -0.2v1 6109 tbl 19 parameter symbol value unit note input hig h leve l v ih 1.8 v input low level v il 0v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v 1 6109 tbl 20 jtag dc operating conditions jtag ac test conditions note : 1. the output impedance of tdo is set to 50 ohms (nominal process) and does not vary with the external resistor connected to zq. note: 1. for sram outputs see ac test load on page 11. jtag input test waveform jtag output test waveform jtag ac test load 6109 drw 23 0.9 v 0.9 v test points 1 .8 v 0v 6109 drw 23a 0.9 v 0.9 v test points 0.9 v 50 ? t do z 0 =50 ? 6109 drw 24 ,
6.42 18 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 parameter symbol min max unit no te tck cyc le time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms inp ut se tup time t mvch 5-ns tms inp ut ho ld time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns cloc k lo w to outp ut valid t clqv 010ns 6109 tbl.21 jtag ac characteristics jtag timing diagram tck tms tdi/ sram inputs tdo t mvch t dvch t svch t chcl t chmx t chdx t chsx t clch 6109 drw 19 t clqv s ram o utputs t chch
6.42 19 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 package diagram outline for 165-ball fine pitch grid array
6.42 20 71p72804 (1m x 18-bit) 71p72604 (512k x 36-bit) commercial and industrialtem perature range 18 mb qdr ii sram burst of 2 ordering information ?qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron techn ology, inc. ? s power xxx speed bq package bq 71p72xxx 250 (1,2) 200 167 6109 drw 15 device type 165 fine pitch ball grid array (fbga) clock frequency in megahertz idt71p72804 1m x 18 qdr ii sram burst of 2 idt71p72604 512k x 36 qdr ii sram burst of 2 x process temperature range commercial (0 o cto+70 o c) blank notes: 1) the 250mhz speed grade is not available in the 512k x36-bit option. 2) industrial temperature range is not available for the 250mhz speed grade. restricted hazardous substance device g x i industrial (-40 o cto+85 o c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or sramhelp@idt.com san jose, ca 95138 408-284-8200 408-284-4532 fax: 408-284-2775 www.idt.com
idt71p72204 (2m x 8-bit), 71p72104 (2m x 9-bit), 71p72804 (1m x 18 x -bit) 71p72604 (512k x 36-bit) 18 mb qdr ii sram burst of 2 commercial temperature range revision history revision date pages description 0 07/20/05 p.1-22 released final datasheet a 04/21/06 p.1-3,7-9 removed x8 and x9 information from the datasheet. 12,15,20 p. 7,11,17 clarified max vddq equals vdd. p.1,7,9,12,20 added industrial temperature to the datasheet. p.20 added green to the datasheet ?restricted hazardous substance device? b 10/13/08 p.20 removed "idt" from orderable part number

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